ICsense files patent on zero-leakage high-voltage switch 

ICsense, leading supplier of analog, mixed signal and high voltage ASICs (Application Specific ICs), has filed another patent to strengthen its portfolio in innovative analog circuits. The invention allows to implement analog, floating high-voltage switches that don’t load its connected lines.

by ICsense

Contrary to existing solutions using large resistances and thereby large time constants, the invention provides a solution with no leakage current and with a small time constant. It is particularly of interest for low-ohmic (low Rdson) switch matrix architectures for the medical, automotive, industrial and consumer markets.


High current switch matrix topologies require the use of low-ohmic (D)MOS switches. The desire to have fast switching times (small time constant, small R1) and low leakage (large R1) cannot be accomplished with a traditional architecture due to the conflicting requirement on R1 (as shown in Fig 1a). “We have designed a novel circuit to eliminate this conflicting requirement and are able to reach fast switching while having virtually zero-leakage. Moreover, in this classical floating pass-switch design the connected lines are loaded when the switch is enabled/disabled. This results in unwanted and inaccurate readings in applications such as high-impedant, high-voltage multiplexers and high-accuracy, high-voltage readouts like piezo-electrical transceivers” says Tim Piessens, CTO of ICsense.

Thanks to a novel circuit ICsense is able to reach fast switching while having virtually zero-leakage.

“We will use this patent to offer ASICs to our customers with increased accuracy and at the same time fast switching and zero-leakage. Our newest patent applies to single MOS switches and to back-to-back topologies that allow full-range isolation,” says Tim.

The design is particularly interesting for applications with low Rdson requirements (<5 Ohm) and heavy constraints on point loading. Additionally, high-voltage switch architectures benefit from the patent because it can cope with negative voltages and polarity changes.

Staying ahead of competition

In the past, ICsense has patented other inventions to stay ahead of competition. To produce more cost-effective wafers, the company patented a circuit (patent nr BE1024217(A1)) which intelligently regulates stacked transistors to provide higher voltage swing (both drive and sense) in plain CMOS processes. The principle uses complex control techniques to guard the SOA (Safe Operating Area). With that invention it is possible to elevate the operational voltage of a plain low-cost CMOS[1] process by a factor of x4. Since 2010, the patent is exploited in ICs which are in mass production by companies such as NVidia.

More information? Please contact: Jeroen Van Ham – Business Development Manager – tel. +32 (0) 16 589 721 – jeroen.vanham@icsense.com


[1] In a standard 0.18um process, ICsense is able to provide 10V operational swing. Bert Serneels, Eldert Geukens, Bram De Muer and Tim Piessens, “A 1.5W, 10V Output Class D Amplifier Using a Boosted Supply from a Single 3.3V Input in standard 1.8V / 3.3V 0.18µm CMOS”, ISSCC Digest of Technical Papers, Feb 2012.