Most SystemVerilog users have a love/hate relationship with SystemVerilog. This hardware description and verification language is really powerful, but also really complex. And it does not protect you at all from making mistakes. Therefor SystemVerilog users will benefit even more from the assistance that Sigasi Studio offers, than their VHDL colleagues. Sigasi Studio helps you focus on what is really important, the design, and makes the compiler understand your intentions.
Based on Sigasi’s experience with providing excellent VHDL support, the Sigasi development team knows how to tackle most challenges in providing a good development environment for SystemVerilog: immediate feedback about syntax errors, autocomplete, open declaration, and so on. Because Sigasi Studio understands what SystemVerilog means, you get very accurate feedback.
Immediate and accurate feedback
The biggest technical challenge was providing good support for SystemVerilog’s Preprocessor. The preprocessor does a textual transformation of SystemVerilog source files. So it can completely rewrite the code that goes into the actual compiler. This preprocessor is stateful and depends on the compilation order. That makes it difficult to keep track of what exactly is going on. To remedy this, Sigasi Studio provides features to easily inspect or preview preprocessed code:
- Source code that is excluded with the Preprocessor is automatically grayed out in the editor.
- The result of Macro’s can be easily previewed in an addition view, or simply by hovering your mouse over the macro.
- Syntax errors are immediately reported
Another example of how Sigasi Studio helps SystemVerilog users, is “include files”. A typical pattern in SystemVerilog is to include sources into other source files (with the Preprocessor). In this case the included file can see everything in the scope of the including file. With an ordinary editor, you have to think about all of this yourself. With Sigasi Studio however, this information is available whenever you require it. For example during autocompletes.
And the nice thing is, this does not require any additional setup. Again, this allows you to focus on the real job: getting your design ready, or making sure it is well tested.
Would you like to try Sigasi Studio on your own SystemVerilog designs, you can request a full trial license on our website www.sigasi.com. This enables you to try all Sigasi Studio’s features on your own projects and feel how Sigasi empowers you. And please tell us all about your experience.