easics Provides Free Tool to Evaluate the Performance of your AI Application on its nearbAI semiconductor IP

embedded AI close to your sensors

nearbAITM is easics’ trademarked product for embedded neural network inference using digital hardware, applied close to your sensors. Its prime application is pattern matching in the supervised learning paradigm. nearbAI consists of two parts: a configurable semiconductor IP core that gets instantiated on your custom ASIC or on an FPGA, and software tools to configure your IP core. It is offered in a licensing model. You can contact us for a free nearbAI Estimator tool license to evaluate the performance of your AI application on the nearbAI IP.

high performance, low power, low cost – your choice

nearbAI targets embedded pattern matching applications close to the sensors, where at least one of the following plays a pivotal role: ultra-low and non-variable inference latency for real-time reaction speeds, ultra-low power consumption for battery-powered operation, lowest hardware component cost for high-volume applications. These applications include novel ultra-low latency AR and VR glasses, battery-powered healthcare wearables, human-in-the-loop medical diagnosis equipment, smart product scanners for retail applications, self-navigating drones, collision-avoidance in vehicles, sophisticated in-line quality inspection in industry 4.0 and earth observation in satellites. Targeted sensors include various types of image sensors, MEMS-microphones, and any novel sensors.

nearbAI Estimator view

evaluate and finetune your application using nearbAI software

The starting point in the nearbAI design flow is a trained neural network model. You can create that using your preferred machine learning framework such as PyTorch, TensorFlow or Keras. The nearbAI Estimator tool reads in your trained model as an ONNX file. Besides that trained model, you input your desired hardware configuration and constraints in the Estimator tool. The latter reflects aspects of your use case such as targeted hardware cost (silicon area), inference speed and latency, and power consumption. The nearbAI Estimator tool shows the latency for each layer of the neural network and highlights any hardware bottlenecks. This allows you to interactively finetune the constraints, evaluate the resulting performance, and arrive at the optimal configuration for your use case, without having to build hardware or run endless simulations. 

nearbAI design flow overview

generate your proprietary nearbAI core

Next, you use the nearbAI Core Generator tool to generate your proprietary nearbAI semiconductor IP core. You further use the nearbAI Network Compiler to generate the microsequence that will sit in memory next to the IP core to run your neural network. Doing ASIC and FPGA design services as well, easics is ready to assist you in integrating nearbAI on your chip.

optimize your return-on-investment.  from any FPGA implementation to your ASIC instantiation.

nearbAI supports efficient hardware mapping on your custom ASIC as well as on Xilinx and Intel FPGAs. Evaluation boards using FPGA or FPGA System-on-Module (SoM) are available, and support plug-in of your ASIC test-chip. The same nearbAI core can run several neural networks using different microsequences. This way, a nearbAI-based product supports field upgrades as well as on-the-fly hot switching between neural networks in a running application. The fine-grained configuration options further allow you to generate several flavors of a nearbAI IP core, such as a low performance and a high performance version. This enables the efficient roll out of a product family. All in all, nearbAI future proofs and optimizes the ROI of your embedded AI developments.

we’ll be back

From 5 till 7 October, easics participated in VISION, the world’s leading trade fair for machine vision in Stuttgart. easics gave live nearbAI demos, and presented it in a talk at the Industrial VISION days, organized by VDMA Machine Vision. On 14 October, easics presented nearbAI at the Bits&Chips Event at the Evoluon in Eindhoven. Upcoming opportunities to meet up and see live demos are the IP-SoC conference in Grenoble on 1 and 2 December 2021, and Embedded World in Nuremberg from 15 till 17 March 2022.



Contact easics for more information and for a free nearbAI evaluation license to try it out yourself:

Email easics directly
More about nearbAI on FPGA
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